1. Field of the Invention
The invention relates to a method for fabricating integrated structure, and more particularly, to a method of forming through-silicon via and redistribution layer (RDL) pattern in one structure.
2. Description of the Prior Art
In electronics, a three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) is a chip with two or more layers of active electronic components (semiconductor devices), integrated both vertically and horizontally into a single circuit. The semiconductor industry is hotly pursuing this promising technology in many different forms. Consequently, the definition is still not yet completely fixed. 3D packaging saves space by stacking separate chips in a single package. This packaging, known as System in Package (SiP) or Chip Stack MCM, does not integrate the chips into a single circuit. The chips in the package communicate with off-chip signaling, much as if they were mounted in separate packages on a normal circuit board. In contrast, a 3D IC is effectively a single chip. All components on the layers communicate with on-chip signaling, whether vertically or horizontally. Essentially, a 3D IC bears the same relation to a 3D package that an SoC bears to a circuit board. An additional advantage of 3D IC is the reduced RC delays (no “slow” off-chip signaling, but only fast on-chip signaling).
When integrated circuits (semiconductor devices) are stacked there is also a need for interconnections that extend through the substrate of the semiconductor devices. Such through-substrate interconnections are also called through-substrate vias. Furthermore, as the location of the through-substrate vias may be different between the respective semiconductor devices there has been a need to make an interfacing layer between the semiconductor devices. This layer is also called the redistribution layer. The redistribution layer is typically manufactured after the back-end-of-line stage (BEOL) of the process. The back-end-of-line stage is the stage in which the interconnect stack of the semiconductor device is manufactured. In other words, the redistribution layer is provided after provision of the passivation layer which is considered to be the last BEOL-step in the manufacturing of a semiconductor device.
The redistribution layer typically comprises at least one redistribution conductor which serves to reroute the location of a through-substrate via of the semiconductor device to another location such that the further semiconductor device, which has a different location of the through-substrate via, can be stacked on the semiconductor device. Another function of the redistribution layer is to make contacting of the through-substrate vias easier (bond-pad function).
Current approach for fabricating TSV conductors and redistribution conductors typically requires multiple patterning process and masks for forming the conductors separately. This approach extends cycle time and affects the overall throughput of the process significantly. Hence, how to effectively improve the current approach for resolving these issues has become an important task in this field.